As the dimensions of integrated circuit devices decrease and the performance increases a larger and larger proportion of the power consumed is lost through such mechanisms as junction leakage, sub-threshold leakage, gate dielectric tunneling leakage, avalanche leakage and drain induced barrier lowering leakage. This non-productive power consumption becomes extremely important in applications where the amount of power available is limited. Therefore, there is a need for a method and electronic device architecture that reduces non-productive power consumption.